DeLeonibus, P. S.: search on Z-Library

The world's largest scientific articles store. 70,000,000+ articles for free.

Don't use scam websites

1

3D nanowire gate-all-around transistors: Specific integration and electrical features

C. Dupré, T. Ernst, V. Maffini-Alvaro, V. Delaye, J.-M. Hartmann, S. Borel, C. Vizioz, O. Faynot, G. Ghibaudo, S. Deleonibus

Journal:

Solid-State Electronics

Year:

2008

Language:

english

File:

PDF, 795 KB

english, 2008

2

A new hot carrier degradation law for MOSFET lifetime prediction

B. Marchand, G. Ghibaudo, F. Balestra, G. Guégan, S. Deleonibus

Journal:

Microelectronics Reliability

Year:

1998

Language:

english

File:

PDF, 287 KB

english, 1998

3

Performance and physics of sub-50 nm strained Si on Si1−xGex-on-insulator (SGOI) nMOSFETs

F. Andrieu, T. Ernst, O. Faynot, O. Rozeau, Y. Bogumilowicz, J.-M. Hartmann, L. Brévard, A. Toffoli, D. Lafond, B. Ghyselen, F. Fournel, G. Ghibaudo, S. Deleonibus

Journal:

Solid-State Electronics

Year:

2006

Language:

english

File:

PDF, 847 KB

english, 2006

4

Alternative CMOS or alternative to CMOS?

Journal:

Microelectronics Reliability

Year:

2001

Language:

english

File:

PDF, 763 KB

english, 2001

5

Silicon-On-Diamond layer integration by wafer bonding technology

Rabarot, M., Widiez, J., Saada, S., Mazellier, J.-P., Lecouvey, C., Roussin, J.-C., Dechamp, J., Bergonzo, P., Andrieu, F., Faynot, O., Deleonibus, S., Clavelier, L., Roger, J.P.

Journal:

Diamond and Related Materials

Year:

2010

Language:

english

File:

PDF, 3.96 MB

english, 2010

6

[IEEE Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. - Grenoble, France (12-16 Sept. 2005)] Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. - Germanium/HfO/sub 2//TiN gate stacks for advanced nodes: influence of surface preparation on MOS capacitor characteristics

Le Royer, C., Garros, X., Tabone, C., Clavelier, L., Morand, Y., Hartmann, J.-M., Campidelli, Y., Kermarrec, O., Loup, V., Martinez, E., Renault, O., Guigues, B., Cosnier, V., Deleonibus, S.

Year:

2005

Language:

english

File:

PDF, 633 KB

english, 2005

7

Isolation design comparisons for 0.5 μm CMOS technology using SILO process

G. Guegan, S. Deleonibus, M. Lerme, J.P. Blanc

Journal:

Microelectronic Engineering

Year:

1992

Language:

english

File:

PDF, 298 KB

english, 1992

8

Multiple gate devices: advantages and challenges

T. Poiroux, M. Vinet, O. Faynot, J. Widiez, J. Lolivier, T. Ernst, B. Previtali, S. Deleonibus

Journal:

Microelectronic Engineering

Year:

2005

Language:

english

File:

PDF, 1.34 MB

english, 2005

9

Raised source/drains for 50 nm MOSFETs using a silane/dichlorosilane mixture for selective epitaxy

A.M. Waite, N.S. Lloyd, K. Osman, W. Zhang, T. Ernst, H. Achard, Y. Wang, S. Deleonibus, P.L.F. Hemment, D.M. Bagnall, A.G.R. Evans, P. Ashburn

Journal:

Solid-State Electronics

Year:

2005

Language:

english

File:

PDF, 330 KB

english, 2005

10

Multigate silicon MOSFETs for 45 nm node and beyond

T. Poiroux, M. Vinet, O. Faynot, J. Widiez, J. Lolivier, B. Previtali, T. Ernst, S. Deleonibus

Journal:

Solid-State Electronics

Year:

2006

Language:

english

File:

PDF, 231 KB

english, 2006

11

On the mobility in high-κ/metal gate MOSFETs: Evaluation of the high-κ phonon scattering impact

Olivier Weber, Mikael Cassé, Laurent Thevenod, Frédérique Ducroquet, Thomas Ernst, Simon Deleonibus

Journal:

Solid-State Electronics

Year:

2006

Language:

english

File:

PDF, 295 KB

english, 2006

12

Experimental determination of the channel backscattering coefficient on 10–70 nm-metal-gate Double-Gate transistors

Vincent Barral, T. Poiroux, M. Vinet, J. Widiez, B. Previtali, P. Grosgeorges, G. Le Carval, S. Barraud, J.L. Autran, D. Munteanu, S. Deleonibus

Journal:

Solid-State Electronics

Year:

2007

Language:

english

File:

PDF, 380 KB

english, 2007

13

Experimental evidence of mobility enhancement in short-channel ultra-thin body double-gate MOSFETs by magnetoresistance technique

W. Chaisantikulwat, M. Mouis, G. Ghibaudo, S. Cristoloveanu, J. Widiez, M. Vinet, S. Deleonibus

Journal:

Solid-State Electronics

Year:

2007

Language:

english

File:

PDF, 284 KB

english, 2007

14

A systematic investigation of work function in advanced metal gate–HfO2–SiO2 structures with bevel oxide

Atsushi Kuriyama, Jérôme Mitard, Olivier Faynot, Laurent Brévard, Laurence Clerc, Amélie Tozzo, Vincent Vidal, Simon Deleonibus, Hiroshi Iwai, Sorin Cristoloveanu

Journal:

Solid-State Electronics

Year:

2007

Language:

english

File:

PDF, 1012 KB

english, 2007

15

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

C. Le Royer, L. Clavelier, C. Tabone, K. Romanjek, C. Deguet, L. Sanchez, J.-M. Hartmann, M.-C. Roure, H. Grampeix, S. Soliveres, G. Le Carval, R. Truche, A. Pouydebasque, M. Vinet, S. Deleonibus

Journal:

Solid-State Electronics

Year:

2008

Language:

english

File:

PDF, 522 KB

english, 2008

16

New floating-body effect in partially depleted SOI pMOSFET due to direct-tunneling current in the partial n+ poly gate

Georges Guegan, R. Gwoziecki, P. Touret, C. Raynaud, J. Pretet, O. Gonnard, G. Gouget, S. Deleonibus

Journal:

Solid-State Electronics

Year:

2009

Language:

english

File:

PDF, 579 KB

english, 2009

17

Method for 3D electrical parameters dissociation and extraction in multichannel MOSFET (MCFET)

C. Dupré, T. Ernst, E. Bernard, B. Guillaumot, N. Vulliet, P. Coronel, T. Skotnicki, S. Cristoloveanu, G. Ghibaudo, O. Faynot, S. Deleonibus

Journal:

Solid-State Electronics

Year:

2009

Language:

english

File:

PDF, 1.15 MB

english, 2009

18

Impact of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories

M. Bocquet, G. Molas, L. Perniola, X. Garros, J. Buckley, M. Gély, J.P. Colonna, H. Grampeix, F. Martin, V. Vidal, A. Toffoli, S. Deleonibus, G. Ghibaudo, G. Pananakakis, B. De Salvo

Journal:

Solid-State Electronics

Year:

2009

Language:

english

File:

PDF, 782 KB

english, 2009

19

A 0.10 μm buried p-channel MOSFET with through the gate boron implantation and arsenic tilted pocket

G. Guegan, S. Deleonibus, C. Caillat, S. Tedesco, B. Dal’zotto, M. Heitzmann, M.E. Nier, P. Mur

Journal:

Solid-State Electronics

Year:

2002

Language:

english

File:

PDF, 460 KB

english, 2002

20

Ultra-thin films and multigate devices architectures for future CMOS scaling

Simon Deleonibus

Journal:

SCIENCE CHINA Information Sciences

Year:

2011

Language:

english

File:

PDF, 1.14 MB

english, 2011

21

Lateral coupling and immunity to substrate effect in ΩFET devices

R. Ritzenthaler, S. Cristoloveanu, O. Faynot, C. Jahan, A. Kuriyama, L. Brevard, S. Deleonibus

Journal:

Solid-State Electronics

Year:

2006

Language:

english

File:

PDF, 487 KB

english, 2006

22

Comparative study of the fabricated and simulated Impact Ionization MOS (IMOS)

F. Mayer, C. Le Royer, G. Le Carval, C. Tabone, L. Clavelier, S. Deleonibus

Journal:

Solid-State Electronics

Year:

2007

Language:

english

File:

PDF, 392 KB

english, 2007

23

Monte-Carlo simulation of MOSFETs with band offsets in the source and drain

M. Braccioli, P. Palestri, M. Mouis, T. Poiroux, M. Vinet, G. Le Carval, C. Fiegna, E. Sangiorgi, S. Deleonibus

Journal:

Solid-State Electronics

Year:

2008

Language:

english

File:

PDF, 198 KB

english, 2008

24

Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI

Emilie Bernard, T. Ernst, B. Guillaumot, N. Vulliet, X. Garros, V. Maffini-Alvaro, P. Coronel, T. Skotnicki, S. Deleonibus

Journal:

Solid-State Electronics

Year:

2008

Language:

english

File:

PDF, 520 KB

english, 2008

25

Integration of CVD silicon nanocrystals in a 32 Mb NOR flash memory

S. Jacob, B. De Salvo, L. Perniola, G. Festes, S. Bodnar, R. Coppard, J.F. Thiery, T. Pate-Cazal, C. Bongiorno, S. Lombardo, J. Dufourcq, E. Jalaguier, T. Pedron, F. Boulanger, S. Deleonibus

Journal:

Solid-State Electronics

Year:

2008

Language:

english

File:

PDF, 907 KB

english, 2008

26

Collapse of MOSFET drain current after soft breakdown

Cester, A., Paccagnella, A., Ghidini, G., Deleonibus, S., Guegan, G.

Journal:

IEEE Transactions on Device and Materials Reliability

Year:

2004

Language:

english

File:

PDF, 568 KB

english, 2004

27

Integration of diamond in fully-depleted silicon-on-insulator technology as buried insulator: A theoretical analysis

Mazellier, Jean-Paul, Faynot, Olivier, Cristoloveanu, Sorin, Deleonibus, Simon, Bergonzo, Philippe

Journal:

Diamond and Related Materials

Year:

2008

Language:

english

File:

PDF, 359 KB

english, 2008

28

[IEEE Tutorial (ICICDT) - Grenoble, France (2008.06.2-2008.06.4)] 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial - 3D CMOS integration: Introduction of dynamic coupling and application to compact and robust 4T SRAM

Batude, P., Jaud, M.-A., Thomas, O., Clavelier, L., Pouydebasque, A., Vinet, M., Deleonibus, S., Amara, A.

Year:

2008

Language:

english

File:

PDF, 1.26 MB

english, 2008

29

[IEEE ESSDERC 2003. 33rd European Solid-State Device Research - ESSDERC '03 - Estoril, Portugal (16-18 Sept. 2003)] Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710) - Raised source/drain (RSD) for 50nm MOSFETs - effect of epitaxy layer thickness on short channel effects

Waite, A.M., Lloyd, N.S., Ashburn, P., Evans, A.G.R., Ernst, T., Achard, H., Deleonibus, S., Wang, Y., Hemment, P.

Year:

2003

Language:

english

File:

PDF, 273 KB

english, 2003

30

[IEEE 31st European Solid-State Device Research Conference - Nuremberg, Germany (2001.9.11-2001.9.13)] 31st European Solid-State Device Research Conference - Gate and Source/Drain Engineering for 50 nm P-Channel MOSFET

Guegan, G., Deleonibus, S., Bertrand, G., Souil, D., Rivallin, P., Tedesco, S., Mur, P., Holliger, P., Nier, M.E.

Year:

2001

Language:

english

File:

PDF, 613 KB

english, 2001

31

[IEEE 2006 International Workshop on Nano CMOS (IWNC) - Mishima, Japan (2006.01.30-2006.02.1)] 2006 International Workshop on Nano CMOS - NanoCMOS devices at the end and beyond the roadmap

Deleonibus, S., De Salvo, B., Clavelier, L., Ernst, T., Faynot, O., Poiroux, T., Vinet, M.

Year:

2006

Language:

english

File:

PDF, 893 KB

english, 2006

32

[IEEE ESSDERC 2003. 33rd European Solid-State Device Research - ESSDERC '03 - Estoril, Portugal (16-18 Sept. 2003)] Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710) - Towards a better EOT - mobility trade-off in high-k oxide/metal gate CMOS devices

Muller, M., Duguay, S., Guillaumot, B., Garros, X., Leroux, C., Tavel, B., Martin, F., Rivoire, M., Delille, D., Boeuf, F., Deleonibus, S., Skotnicki, T.

Year:

2003

Language:

english

File:

PDF, 312 KB

english, 2003

33

[Japan Soc. Appl. Phys 1999 Symposium on VLSI Technology. Digest of Technical Papers - Kyoto, Japan (14-16 June 1999)] 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325) - 65 nm physical gate length NMOSFETs with heavy ion implanted pockets and highly reliable 2 nm-thick gate oxide for 1.5 V operation

Caillat, C., Deleonibus, S., Guegan, G., Tedesco, S., Dal'zotto, B., Heitzmann, M., Martin, F., Mur, P., Marchand, B., Balestra, F.

Year:

1999

Language:

english

File:

PDF, 197 KB

english, 1999

34

In-depth characterization of the hole mobility in 50-nm process-induced strained MOSFETs

Andrieu, F., Ernst, T., Ravit, C., Jurczak, M., Ghibaudo, G., Deleonibus, S.

Journal:

IEEE Electron Device Letters

Year:

2005

Language:

english

File:

PDF, 155 KB

english, 2005

35

[IEEE ESSDERC 2003. 33rd European Solid-State Device Research - ESSDERC '03 - Estoril, Portugal (16-18 Sept. 2003)] Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710) - SiGe channel p-MOSFETs scaling-down

Andrieu, F., Ernst, T., Romanjek, K., Weber, O., Renard, C., Hartmann, J.-M., Toffoli, A., Papon, A.-M., Truche, R., Holliger, P., Brevard, L., Ghibaudo, G., Deleonibus, S.

Year:

2003

Language:

english

File:

PDF, 310 KB

english, 2003

36

[IEEE Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. - Grenoble, France (12-16 Sept. 2005)] Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005. - In-depth study of strained SGOI nMOSFETs down to 30nm gate length

Andrieu, F., Ernst, T., Faynot, O., Rozeau, O., Bogumilowicz, Y., Hartmann, J.-M., Brevard, L., Toffoli, A., Lafond, D., Dansas, H., Ghyselen, B., Fournel, F., Ghibaudo, G., Deleonibus, S.

Year:

2005

Language:

english

File:

PDF, 709 KB

english, 2005

37

[IEEE Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. - Kyoto, Japan (June 14-16, 2005)] Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. - Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs

Andrieu, F., Ernst, T., Lime, F., Rochette, F., Romanjek, K., Barraud, S., Ravit, C., Boeuf, F., Jurczak, M., Casse, M., Weber, O., Brevard, L., Reimbold, G., Ghibaudo, G., Deleonibus, S.

Year:

2005

Language:

english

File:

PDF, 434 KB

english, 2005

38

[IEEE 2011 IEEE International Symposium on Circuits and Systems (ISCAS) - Rio de Janeiro, Brazil (2011.05.15-2011.05.18)] 2011 IEEE International Symposium of Circuits and Systems (ISCAS) - 3D monolithic integration

Batude, P., Vinet, M., Pouydebasque, A., Le Royer, C., Previtali, B., Tabone, C., Hartmann, J.-M., Sanchez, L., Baud, L., Carron, V., Toffoli, A., Allain, F., Mazzocchi, V., Lafond, D., Deleonibus, S.

Year:

2011

Language:

english

File:

PDF, 827 KB

english, 2011

39

Ultimate sub-25 nm gate length NMOSFETs transport at 293 and 77 K

G Bertrand, S Deleonibus, D Souil, C Caillat, G Guegan, S Tedesco, M Heitzmann, P Mur, F Balestra

Journal:

Superlattices and Microstructures

Year:

2000

Language:

english

File:

PDF, 618 KB

english, 2000

40

A fully scaled 0.5μm CMOS process for fast random logic

M. Lerme, G. Guegan, S. Deléonibus, F. Martin, M. Heitzmann, F. Vinet, C. Jaffard, M. Belleville, M. Guerin, G. Reimbold, C. Leroux

Journal:

Microelectronic Engineering

Year:

1991

Language:

english

File:

PDF, 170 KB

english, 1991

41

Optimisation of isolation for 0.5 μm CMOS technology using SILO process with R.T.N. of silicon

G. Guegan, S. Deleonibus, M. Lerme, G. Reimbold, P. Molle

Journal:

Microelectronic Engineering

Year:

1991

Language:

english

File:

PDF, 173 KB

english, 1991

42

A GIGABIT scalable SILO field isolation using Rapid Thermal Nitridation (RTN) of silicon

Journal:

Microelectronic Engineering

Year:

1992

Language:

english

File:

PDF, 323 KB

english, 1992

43

Study of SiO2/Si interface states in MOS devices by surface charge spectroscopy. Application to rapid thermal nitridation of silicon

A. Ermolieff, S. Deleonibus, S. Marthon, B. Blanchard, J. Piaguet

Journal:

Journal of Electron Spectroscopy and Related Phenomena

Year:

1994

Language:

english

File:

PDF, 610 KB

english, 1994

44

Reduction of fixed charges in atomic layer deposited Al2O3 dielectrics

J. Buckley, B. De Salvo, D. Deleruyelle, M. Gely, G. Nicotra, S. Lombardo, J.F. Damlencourt, Ph. Hollinger, F. Martin, S. Deleonibus

Journal:

Microelectronic Engineering

Year:

2005

Language:

english

File:

PDF, 429 KB

english, 2005

45

In-depth investigation of the mechanisms impacting C-V/G-V characteristics of Ge/GeON/HfO2/TiN stacks by electrical modeling

P. Batude, X. Garros, L. Clavelier, C. Le Royer, J.M. Hartmann, V. Loup, P. Besson, L. Vandroux, S. Deleonibus, F. Boulanger

Journal:

Microelectronic Engineering

Year:

2007

Language:

english

File:

PDF, 464 KB

english, 2007

46

Evaluation of HfAlO high-k materials for control dielectric applications in non-volatile memories

G. Molas, M. Bocquet, J. Buckley, H. Grampeix, M. Gély, J.P. Colonna, F. Martin, P. Brianceau, V. Vidal, C. Bongiorno, S. Lombardo, G. Pananakakis, G. Ghibaudo, B. De Salvo, S. Deleonibus

Journal:

Microelectronic Engineering

Year:

2008

Language:

english

File:

PDF, 333 KB

english, 2008

47

Activation level in boron-doped thin germanium-on-insulator (GeOI): Extraction method and impact of mobility

Louis Hutin, Stéphane Koffel, Cyrille Le Royer, Laurent Clavelier, Pascal Scheiblin, Vincent Mazzocchi, Simon Deleonibus

Journal:

Materials Science in Semiconductor Processing

Year:

2008

Language:

english

File:

PDF, 358 KB

english, 2008

48

Electrical properties of Si1−yCy/Si/SiO2 interface for sub 50 nm strained-channel nMOSFETs

F. Ducroquet, T. Ernst, O. Weber, J.-M. Hartmann, V. Loup, P. Besson, L. Brévard, J.L. Di Maria, S. Deleonibus

Journal:

Applied Surface Science

Year:

2004

Language:

english

File:

PDF, 125 KB

english, 2004

49

A new memory concept: the nano-multiple-tunnel-junction memory with embedded Si nano-crystals

D Deleruyelle, C Le Royer, B DeSalvo, G Le Carval, M Gely, T Baron, J.L Autran, S Deleonibus

Journal:

Microelectronic Engineering

Year:

2004

Language:

english

File:

PDF, 494 KB

english, 2004

50

Strain and channel engineering for fully depleted SOI MOSFETs towards the 32 nm technology node

F. Andrieu, O. Weber, T. Ernst, O. Faynot, S. Deleonibus

Journal:

Microelectronic Engineering

Year:

2007

Language:

english

File:

PDF, 1.54 MB

english, 2007

To build up a library is to create a life. It’s never just a random collection of books.

— Carlos María Domínguez

Official channel

Z-Library Desktop Launcher

Z-Library Since 2009 support@z-lib.do

EnglishРусскийEspañolItalianoελληνικάاللغة العربيةBahasa IndonesiaBahasa Malaysiaहिन्दीDeutschFrançaisPortuguêsУкраїнськаPolski中文繁體中文日本語Tiếng ViệtAzərbaycan DiliՀայոց լեզուภาษาไทยTürk Diliქართველიবাংলাپښتوతెలుగుاردو한국어SrpskiБългарски